The caching invalidation guidelines from the AMD-Vi specification (48882—Rev
3.07-PUB—Oct 2022) is incorrect on some hardware, as devices will malfunction
(see stale DMA mappings) if some fields of the DTE are updated but the IOMMU
TLB is not flushed.
Such stale DMA mappings can point to memory ranges not owned by the guest, thus
allowing access to unindented memory regions.
References
Link | Resource |
---|---|
https://xenbits.xenproject.org/xsa/advisory-442.html | Vendor Advisory |
Configurations
History
No history.
Information
Published : 2024-01-05 17:15
Updated : 2024-01-11 15:57
NVD link : CVE-2023-34326
Mitre link : CVE-2023-34326
CVE.ORG link : CVE-2023-34326
JSON object : View
Products Affected
xen
- xen
CWE